The present invention relates to a method for manufacturing a nonvolatile semiconductor memory. More specifically, the present invention relates to a method for manufacturing a nonvolatile semiconductor memory having a tunnel oxide film, floating gate, insulating film and control gate stacked in this order on a semiconductor substrate.
Conventionally, a nonvolatile semiconductor memory of this kind is manufactured according to a process order shown in FIGS. 10A to 10C and 11A to 11C. FIGS. 10A to 10C are cross sections in an Xxe2x80x94X direction in FIG. 1A. FIGS. 11A to 11C are cross sections in a Yxe2x80x94Y direction in FIG. 1A. Here, FIG. 1A is a plan view of a nonvolatile semiconductor memory according to an embodiment of the present invention, but FIG. 1A is also used to explain a conventional technique.
First, as shown in FIGS. 10A and 11A, a tunnel oxide film 2 having a thickness of 10 nm is formed on a semiconductor substrate 1 by thermal oxidation. Then, a first conductive layer 3 having a thickness of 100 nm is deposited. The first conductive layer 3 is composed of polysilicon as a material of a floating gate. Subsequently, the tunnel oxide film 2 and the first conductive layer 3 are patterned in stripes extending in the Yxe2x80x94Y direction. At this time, a size of the first conductive layer 3 in the Xxe2x80x94X direction (channel direction) is set so as to match a size of the floating gate to be finally formed.
Subsequently, phosphorus (P) ion implantation is performed under conditions of an acceleration energy of 50 keV and a dose of 3.0xc3x971013 ions/cm2 by using the first conductive layer 3 patterned in stripes as a mask so as to form an n-type low-concentration impurity diffusion layer 4 in a surface region of the semiconductor substrate 1 between the first conductive layers 3.
Subsequently, photolithography is performed to form a photoresist (not shown) in stripes extending in the Yxe2x80x94Y direction. Arsenic (As) ion implantation is performed by using this photoresist and the first conductive layer 3 patterned in stripes as masks under conditions of an acceleration energy 15 keV and a dose of 4.5xc3x971015 ions/cm2 so as to form an n-type high-concentration impurity diffusion layer 5 in the low-concentration impurity diffusion layer 4. These impurity diffusion layers 4, 5 are used as a source/drain region i.e. a bit line.
Subsequently, as shown in FIG. 10B, an interlayer insulating film 6 is deposited on these layers in a thickness exceeding the thickness of the first conductive layer 3 by the CVD method to sufficiently cover the first conductive layer 3. Subsequently, an etchback is performed to planarize the surface of the interlayer insulating film 6, and the interlayer insulating film 6 is so left as to be embedded between the first conductive layers 3.
Subsequently, as shown in FIGS. 10C and 11C, a first insulating film 7 composed of, for example, an ONO film (oxide film/nitride film/oxide film) is deposited and then a second conductive layer 8 composed of polysilicon having a thickness of 200 nm is deposited. Then, photolithography is performed to form a photoresist (not shown) in stripes extending in the Xxe2x80x94X direction. The second conductive layer 8, the first insulating film 7 and the first conductive layer 3 are etched and patterned by using this photoresist as a mask. Consequently, there are formed a control gate in stripes composed of the second conductive layer 8, the first insulating film 7 in stripes composed of the ONO film and a floating gate in a rectangular solid composed of the first conductive layer 3.
In this state, as shown in FIG. 12A which is an enlarged view of a portion P enclosed with a broken line in FIG. 11C, a portion of the tunnel oxide film 2 immediately below a sidewall of the floating gate 3 includes damages (shown with x). This damaged portion easily serves as a path for electrons to leak from the floating gate 3 to the semiconductor substrate 1 side during an operation of a finished product. Accordingly, as shown in FIG. 12B, thermal oxidation is performed, for example, in an oxygen atmosphere at 850xc2x0 C. for 20 minutes so as to form a silicon oxide film 11 having a thickness of 20 to 30 nm on the sidewalls of the floating gate 3 composed of polysilicon and the control gate 8.
Subsequently, as shown in FIG. 11C, boron (B) ion implantation is performed under conditions of an acceleration energy 40 keV and a dose of 1.0xc3x971013 ions/cm2 by using the control gate 8 as a mask so as to form a p-type element separating impurity diffusion layer 9 in a surface region of the semiconductor substrate 1 between the control gates 8.
Then, an interlayer insulating film is deposited on this layer by a known method, a contact hole is opened in this interlayer insulating film and then interconnect lines are further formed to complete a nonvolatile memory, none of which are shown.
However, in the above conventional manufacturing method, as shown in FIG. 7 which is an enlarged view of a portion P1 enclosed with a broken line in FIG. 12A, a grain boundary 13 between polysilicon grains 12 of the floating gate 3 is easily oxidized during the process of oxidizing the sidewalls of the floating gate 3 and the control gate 8 because the silicon oxide film 11 is formed on the sidewalls of the floating gate 3 and the control gate 8, resulting in localized nonuniform oxidation. As a result, a localized electric field concentration occurs between the floating gate 3 and the source/drain region in the semiconductor substrate 1 during an operation of the nonvolatile memory. Thus, a problem arises that equal FN (Fowler-Nordheim) currents do not flow through the tunnel oxide film in each memory cell during a write operation, thereby increasing a variation in threshold voltages between the memory cells.
As known, usually, data is simultaneously written in memory cells on the same word line (control gate). As evident from FIG. 9 showing a threshold voltage distribution after a write operation in memory cells on the same word line, there is a large variation of 2.2 V in threshold voltages among nonvolatile memory cells on the same word line, which cells are manufactured by the above method.
In order to even the threshold voltages during a write operation, a verify write operation for each bit is usually performed. However, when there is a large variation in threshold voltages among memory cells on the same word line as described above, the number of steps during the write operation needs to be increased, resulting in a longer write time.
Furthermore, when data is written in this semiconductor memory, a high voltage is also applied to a nonselected memory cell on the same word line. Therefore, electrons in a floating gate of the nonselected cell are decreased (gate disturbance). When the variation in threshold voltages is large among memory cells on the same word line, a memory cell in which data can be particularly rapidly written is easily affected by the gate disturbance.
To solve the above problem, as shown in FIG. 13, a technique has been proposed wherein a tunnel oxide film 24, a floating gate electrode 25 and a source region 22 are formed on the semiconductor substrate 21, thereafter a material of the floating gate electrode 25 is isotropically etched and then oxidized (Japanese Patent Laid-Open Publication H9-17890). With this technique, a corner portion of the floating gate 25 on the semiconductor substrate 21 is made round while an oxide film 28 is formed. However, this technique cannot control the localized nonuniform oxidation attributable to polysilicon grains constituting the floating gate electrode 25. As a result, an electric field concentration cannot be prevented and a variation in FN currents occurs for each memory cell and the variation in threshold voltages between memory cells is increased. Furthermore, since controlling of an etching rate in the isotropic etching process is difficult, a large margin is required, thereby hindering future miniaturization. Furthermore, the size of the floating gate changes depending on the etching rate in the isotropic etching process and the channel length and the channel width change, which also causes a variation in threshold voltage.
Accordingly, an object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory by which various problems such as gate disturbance can be solved by suppressing variations in threshold voltages of the nonvolatile semiconductor.
To achieve the above object, the present invention provides a method for manufacturing a nonvolatile semiconductor memory wherein memory cells each having a tunnel oxide film, a floating gate, a first insulating film and a control gate stacked in this order are formed in a matrix on a semiconductor substrate, the method comprising the steps of:
forming the tunnel oxide film on the semiconductor substrate;
forming a first conductive layer to be used as a material of the floating gate on the tunnel oxide film;
patterning the first conductive layer in stripes extending in one direction;
forming a source/drain region in a surface of the semiconductor substrate by using the first conductive layer as a mask;
forming the first insulating film on the first conductive layer;
forming a second conductive layer on the first insulating film;
forming the control gate in stripes composed of the second conductive layer, the first insulating film in stripes and the floating gate in a rectangular solid composed of the first conductive layer by etching with a mask in stripes extending a direction perpendicular to the first conductive layer;
removing a portion of the tunnel oxide film immediately below a sidewall of the floating gate by isotropical etching; and
depositing a second insulating film on the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film to be covered with the second insulating film.
According to the present invention, a portion of the tunnel oxide film immediately below the sidewall of the floating gate is removed by isotropic etching. This removes a damaged layer generated in the tunnel oxide film during the process of forming the floating gate. Therefore, there would be no path for electrons to leak from the floating gate to the semiconductor substrate side during an operation of a finished product. Furthermore, when the second insulating film is deposited and then thermal oxidation is performed to oxidize the sidewall of the floating gate via the second insulating film, uniform oxidation occurs at an interface between the floating gate and the surrounding insulating film. Therefore; equal FN (Fowler-Nordheim) currents flow through the tunnel oxide film in each memory cell during a write operation. Thus, compared with a conventional memory, the variation in threshold voltages among memory cells, for example, memory cells on the same word line is reduced.
As a result, since there is no variation in threshold voltages on the same word line, the number of steps during the write operation can be reduced, thereby shortening the write time.
In addition, since memory cells on the same word line wherein data is written particularly rapidly can be erased, the number of memory cells affected by gate disturbance can be reduced.
Furthermore, since the second insulating film is formed in a space portion of the floating gate, miniaturization is not hindered.
Still furthermore, the size of the floating gate does not change depending on isotropic etching of the tunnel oxide film after formation of the floating gate or deposition of the second insulating film. Therefore, there is no problem of a short channel effect due to the channel length or a narrow channel effect due to the channel width and no variation in threshold voltages attributable to them occurs.
In one embodiment of the present invention, after the second insulating film is deposited, thermal oxidation is performed to oxidize the sidewall of the floating gate via the second insulating film.
According to the embodiment, uniform oxidation occurs at an interface between the floating gate and the surrounding insulating film. Therefore, equal FN (Fowler-Nordheim) currents flow through the tunnel oxide film in each memory cell during a write operation. Thus, compared with a conventional memory, the variation in threshold voltages between memory cells, for example, memory cells on the same word line is reduced.
In one embodiment of the present invention, isotropic etching of the tunnel oxide film after formation of the floating gate is performed by wet etching using a fluorinated acid.
According to the embodiment, a portion of the tunnel oxide film immediately below a sidewall of the floating gate can be precisely removed by wet etching using the fluorinated acid.
In one embodiment of the present invention, the second insulating film is a silicon oxide film formed by chemical vapor deposition
According to the embodiment, the sidewalls of the control gate, the first insulating film, the floating gate and the tunnel oxide film can be favorably covered with the second insulating film.